The present invention relates generally to a semiconductor memory device, and more particularly, to an impedance calibration circuit for impedance matching between a semiconductor memory device and an external device, a semiconductor memory device including the impedance calibration circuit at an input/output terminal thereof, and a layout method of an internal resistance in the impedance calibration circuit.
Typically, a high speed semiconductor memory device such as a DDR3 is provided with an impedance calibration circuit that calibrates an on die termination (ODT) value in response to process, voltage, and temperature (PVT) variation.
The impedance calibration circuit calibrates the impedance of an internal resistance by utilizing a resistance connected to the outside of the memory chip and provides a code signal having the calibrated information to a data input/output (I/O) driver. Then, the driving level of the data I/O driver is adjusted using the code signal and impedance matching with an external device that interfaces data is thereby completed.
The impedance calibration circuit includes a driver provided with a plurality of legs in order to calibrate the impedance of the internal resistance, and the code signal having the impedance calibration information is generated and outputted by comparing the impedance of the legs to the impedance of the external resistance.
The data I/O driver also includes a plurality of legs for adjusting the driving force in response to the code signal. The impedance corresponding to the data outputted to outside the memory device is calibrated as the impedance of the legs varies in response to the code signal.
However, the structure of conventional semiconductor memory devices tends to cause an impedance mismatch between the impedance calibration circuit and the data I/O driver. It is difficult to detect and calibrate for this impedance mismatch, and therefore the generated impedance mismatch can be problematic.
Specifically, in a conventional data I/O driver, the legs have various resistance values in order to support various internal resistance modes. To the contrary, a conventional impedance calibration circuit only includes legs for comparison with an external resistance. That is, unlike the data I/O driver, the legs of the conventional impedance calibration circuit have only a single resistance value, with the single resistance value being the same resistance value as the external resistance.
Therefore, in a conventional semiconductor memory device there is a high probability that an impedance mismatch will occur, since the legs of the impedance calibration circuit and the legs of the data I/O driver have different layout structures.
Additionally, both the conventional impedance calibration circuit and the conventional data I/O driver include a pull-up driver and a pull-down driver. The pull-up driver of the impedance calibration circuit is connected to a pin of the external resistance. The pull-down driver of the impedance calibration circuit is not directly connected to the pin of the external resistance, and is instead connected to the pull-up driver through an internal node. To the contrary, in a conventional data I/O driver, the pull-up driver and pull-down driver are both connected to an external data input/output pin.
The difference in the pull-up and pull-down drivers of the conventional data I/O driver and the conventional impedance calibration circuit are another example of a differing structure that causes a problem. The difference in structure of the connection to an external pin of the driver of the impedance calibration circuit and the data I/O driver results in a high probability that an impedance mismatch will be generated.
To summarize, an impedance mismatch is generated between the impedance calibration circuit and the data I/O driver of the conventional device due to the difference in layout structure and connection between the impedance calibration circuit and the data I/O driver.
This impedance mismatch is problematic, in that an impedance calibration value DQ_CAL may differ significantly from a target value TARGET upon pull-down driving of the data I/O driver. This difference is shown in illustration (a) of FIG. 1.
For reference, in illustration (a) and (b) of FIG. 1, ‘ZQ’ indicates the impedance of the impedance calibration circuit before the impedance calibration, ‘ZQ_CAL’ indicates the impedance of the impedance calibration circuit after the impedance calibration, and ‘DQ’ indicates impedance of the data I/O driver before the impedance calibration.
In requires much time and effort to fix the calibration problem caused by the conventional impedance calibration circuit which includes legs having only a single resistance value and which calibrates the impedance by comparing these legs only to an external resistance.